英语翻译请既懂英语又懂点儿verilog或vhdl语言的高手帮忙翻译一下以下内容：CAUSE:In a conditio

英语翻译
请既懂英语又懂点儿verilog或vhdl语言的高手帮忙翻译一下以下内容：
CAUSE:In a conditional statement at the specified location in a Verilog Design File (.v),you specified a condition that Quartus II Integrated Synthesis cannot use to classify the edges in the enclosing always construct's event control.When an event control contains multiple edges,Quartus II Integrated Synthesis distinguishes the asynchronous control signals from the clock by analyzing the conditional statements in the always construct.For example,the following code fragment contains an always construct whose event control contains three edges---two asynchronous resets and a clock.
always @ (posedge clk or posedge rst1 or posedge rst2) begin
if ( rst1 || rst2 )
q
太简短了！分可以加！
ps:z919z你搞毛啊！我在回答一楼的问题啊！他不是说分太低了吗！我来这就是要虚心学习的，这不用你说！
我就是想请个高人逐字逐句的翻译，不要大概的，大概的我也懂，求学就是要精要细！我说简短并没有冒犯的意思，是我个人的要求（难道我来提问，提个要求也不行吗？那不就成了随便乱答都是正确答案囖）！
不过你放心，如果期限内真没高人出现，我也会选你，能者居之！