怎样用VHDL设计含有异步清零和同步时钟使能的10位加法计数器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add is
port(clr,en,clkin:in std_logic; ---------清零,使能及触发时钟
a,b:in std_logic_vector(9 downto 0);---------加数
c:out std_logic_vector(9 downto 0);----------和
ci:out std_logic ---------进位
);
end add;
architecture arch of add is
---------;
signal reg:std_logic_vector(10 downto 0):="00000000000";
----------------------------------------------------------------------------
begin
----------------
process(clr,clkin,en,a,b)
begin
if(clr='0') then --------------异步清零
reg